(1) Field of the Invention
The invention generally relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a field-effect transistor (FET) having a recessed gate structure in the manufacture of integrated circuits.
(2) Description of Prior Art
A device prevalent in high-speed integrated circuits is the so-called metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET comprises three electrodes: a source, a drain and a gate. The heavily doped source and drain (S/D) regions are separated by a lightly doped channel. If the S/D are n-type material, then the channel is p-type and the device is an NMOS transistor. Conversely, if the S/D are p-type material, then the channel is n-type and a PMOS transistor results. The gate electrode is positioned over, but electrically insulated from the channel. By applying a voltage to the gate electrode, the conductivity of the channel is affected, thus a voltage on the gate can control the current between the source and drain. By implanting dopant ions into the channel, the threshold or xe2x80x9cturn-onxe2x80x9d gate voltage can be tailored to the required level.
As integrated circuit device dimensions are reduced, parasitic effects become a challenge. In MOSFET devices, as the distance between the source and drain (channel length) is reduced, punch-through, hot-carrier effect, and interelectrode capacitance become factors that degrade performance.
As the channel length is decreased, a voltage applied to the drain electrode can result in conduction between the source and drain without a voltage applied to the gate. This punch-through effect reduces the control the gate electrode has over the drain current. Typically, a punch-through implantation is performed (along with the threshold adjust implantation) prior to formation of any of the gate structure to counter the effects of the short channel.
To reduce the hot carrier effect, the S/D regions are formed with two dopant levels. Typically, lightly doped S/D regions are formed by ion implantation using the gate as a mask. This is followed by the formation of gate sidewall spacers to, in effect, widen the gate mask. This is followed by a second more heavily doped S/D implantation. The presence of a lightly doped S/D concentration near the gate electrode minimizes the hot carrier effect. Alternately, a lightly doped envelope for the heavily doped S/D junctions may be formed by a faster diffusing dopant ion implantation with a lower dose, followed by a heavy ion implantation at a higher dose.
Capacitance between the drain and substrate is inversely proportional to the width of the depletion region between them. For a specific S/D dopant concentration, the depletion region width decreases as the substrate dopant concentration increases. Thus, as the punch-through implantation increases the substrate dopant concentration, the depletion region width shrinks, and the drain capacitance increases. This increase in drain capacitance limits the speed at which the device and the integrated circuit will switch.
One method of reducing the aforementioned parasitic effects is to use a device with a recessed channel. The recessed channel reduces punch-through, and in some cases, the punch-through implantation step is eliminated and capacitance is reduced. Several methods of forming recessed channels have been described. U.S. Pat. No. 5,814,544 to Huang teaches a method of forming a recessed channel where a silicon nitride layer with a gate opening is patterned. Mask oxide is then grown in the exposed gate opening consuming some of the silicon. The S/D implantation is performed using the mask oxide in the gate opening as a mask. The oxide is then removed leaving a recessed channel area. U.S. Pat. No. 5,599,728 to Hu et al. teaches a method of forming a recessed gate by forming a trench in a silicon nitride spacer. A wet oxidation is performed creating the recessed gate. U.S. Pat. No. 5,610,090 to Jo teaches a method incorporating reactive ion etching (RIE) to form a non-symmetrical recessed gate. U.S. Pat. No. 5,270,228 to Ishikawa teaches a method of forming a two-level recessed gate using a single lithographic and etch step.
A principal object of the present invention is to provide a method for forming a self-aligned, recessed channel, MOSFET device.
A second object of the present invention is to provide a method for forming a self-aligned, recessed channel, MOSFET gate electrode.
Another object of the present invention is to provide a method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel effects, including punch through, hot carrier effect and increased inter-electrode capacitance.
Another object of the present invention is to provide a method for forming a self-aligned, recessed channel, MOSFET gate electrode that alleviates the problems due to short channel effects, including punch through, hot carrier effect and increased inter-electrode capacitance.
These objects are achieved using a process where the gate structure of a MOSFET, comprising a gate dielectric covered by a gate electrode, is formed in a recess in the substrate. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched using photolithographic techniques to expose the substrate and a portion of the STI region. The surface is etched in the active area and the mask oxide layer is eroded away while forming a gate recess in the unmasked area. The exposed portion of the STI region will also be etched.
A thin pad oxide layer is grown overlying the surface followed by deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is then planarized exposing the pad oxide layer. Additional oxide is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide is grown causing the pad oxide layer to further thicken. This forms a tapered oxide layer along the sidewalls of the gate recess. The remaining silicon nitride layer is then removed, re-opening the gate recess. A threshold adjust and punch-through implantation is performed into the substrate below the gate recess. The tapered oxide layer on the gate recess sidewalls protects the implantation from reaching areas laterally outside the forthcoming gate structure. Next, the pad oxide layer is isotropically etched to remove the oxide at the bottom of the gate recess. A gate dielectric is then grown in the bottom of the gate recess. This is followed by a deposition of gate polysilicon covering the top surface and filling the gate recess. The top surface is again planarized to expose the top of the substrate. This completes the formation of the recessed gate structure.
To complete the formation of the transistor and make interconnections, a screen oxide layer is deposited followed by light and heavy dose implantations for double implanted drain (DID), and annealing. An inter-electrode dielectric layer is deposited covering the top surface. Contact holes are then patterned in the dielectric layer. A metalization layer is deposited overlying the surface and filling the contact holes. The metalization layer is then patterned and a passivation layer is deposited completing the fabrication and interconnection of the MOS transistor device.